Improving the clock signal on my 8-bit “Hol-1” CPU.
As my homebrew 8-bit CPU takes shape I find I’m continually fighting temptation to re-design the boards that have been created so far. I realise though that that would be unproductive as no sooner had I created a version 2 of a board then I’d get nagging doubts about what I could do with a version 3. So I’m resisting temptation and continuing to make progress, however slowly, to complete Hol-1. All ideas for improvements will be used to build Hol-2 in the future.
However, as Hol-1 grows I’ve started to experience problems with the clock signal so some interim tweaks are needed to resolve them.
The clock-source and clock-control circuits were created as two separate boards. These are a much smaller size than the rest of the boards in Hol-1 but that’s not the problem. It’s just an annoyance so I’ll ensure Hol-2 sticks to a common board size.
The clock-source circuit produced two outputs: a single step signal via a tactile button and a stream of clock pulses of variable frequency adjusted via a potentiometer.
The clock-control circuit took both the clock-source outputs as inputs and enabled you to choose which one to output to Hol-1 via a toggle switch.
Together these clock circuits can operate Hol-1 from a complete halt up to a speed of 510Hz. An alternative external clock signal can also be used to substitute the clock-source outputs to enable faster Hol-1 operation and the upper limit has yet to be determined.
Clock Signal Problem:
As Hol-1 grows I’ve noticed problems with the prototype program counter (PC) giving unreliable results. Other than when it’s being set to a specific value (with a good old GOTO or JMP statement) the PC should basically count the clock pulses but it’s intermittently missing signals or providing multiple counts on a single clock pulse.
‘Intermittent’ is never something you want to have associated with a problem, so I started by checking the clock signal with an oscilloscope.
The rising edge of the clock pulse was as good as I could hope for at 8.4nS with minimal overshoot or ripple once it had transitioned from a Low to a High state. But was the Low state low enough and the High state high enough?
An easy misconception about the TTL logic of this 74LS family is that Low is 0V and High is 5V. Actually any signal from 0V to 0.8V should register as Low and the threshold for a logic High is 2V up to 5V.
So my 0.2V logic Low on the clock signal was fine but the 2.2V High was a concern. It’s too close to the 2V threshold for a TTL High signal so any weaker and a pulse wouldn’t be counted.
Worse was to be found on the falling edge if the clock signal. The transition from High to Low took 139nS, over 16 times slower than the clock’s rising edge. According to datasheets for the 74LS family of ICs the logic signal fall time should be within 50nS.
The signal also plateaus at around 1.5V for most of that fall time. 1.5V is in TTL no-man’s-land as it could be taken as a High or a Low and the longer a signal spends at that level the more likely it could wobble between the two logic states and be counted as multiple pulses.
So the clock signal peak voltage was too low at 2.2v and the transition from a high to low signal was taking too long at 139nS.
A weak output signal could be caused by a poor solder joint on the Vcc supply or ground pins of a TTL chip. But the investigation of this problem didn’t require a careful inspection of the clock-control circuit build, the cause was obvious when checking the schematic.
The clock output from the clock-control circuit is sourced from pin-10 of the 74LS04 hex inverter. This buffer IC will clean up the incoming signal to pin-11 and provide a strong TTL output signal on pin-10. But the output socket is then being tied to ground via a hard-wired green LED!
This will cause a voltage drop on the outgoing signal and the LED switching was no doubt the cause of the delayed fall time on the signal. Had I used a series resistor with that LED then the issue would have been less noticeable (yet still not ideal) but such a resistor wasn’t necessary to limit the current from the TTL output.
Removing the LED would work but it is useful to show the clock signal pulsing.
As there are unused gates on the 74LS04 hex buffer then the cleanest option was to feed the incoming signal to two of the inverter buffers. Then feed the clock-out socket from one of those and the LED from the other.
As the circuit had already been built the simplest modification was to link pin-11 to pin-13. This fed two of the buffers and their outputs on pin-10 and pin-12 could feed the clock-out socket and the LED respectively.
Here is a close-up of that section of the clock-control circuit showing the new layout. The rest of that board remains unchanged.
A fresh snapshot of the clock signal with the same timebase as the earlier stepped fall shows that this has now been resolved. The fall time has been reduced from 139nS to 6.8nS and without any plateauing at 1.5v. It does show a small over-shoot at the bottom of the fall but I expect that to be resolved once the signal is connected to Hol-1.
The volts per division in this final image have been increased from the original 500mV scale to 1V per division. This enables the full high to low signal fall to be captured and shows that the clock high is now close to 4V. Much better than the original 2.2V.
Apologies to anyone following my Hol-1 build and now having to apply this fix but at least it’s a fairly quick and unmessy solution. It’s also a reminder that I’m learning as I go!
From Fritzing to KiCad:
Fritzing has been a nice tool to work with to develop these Hol-1 circuit boards but it has its limitations. The main issues have been version control, ease of sharing and limited functionality of the schematic editor.
I have therefore taken the time to convert all the board designs to KiCad. As KiCad stores designs in readable ASCII text files it enables me to use Git for version control. Its design tools are more feature rich (and therefore more complicated) e.g. enabling the use of a single line to represent a bus and segmented schematics joined by global net labels.
I shall continue to use double-sided perfboard with a fixed grid of vias and I find these easier to layout and picture in Fritzing. So KiCad isn’t better in every respect.
Neither tool caters properly for this kind of construction so I have to layout ‘PCBs’ on a fixed 2.54mm grid.
All Hol-1 circuit designs have now been published on my GitHub site: https://github.com/agben
Categorised as: Homebrew 8-Bit CPU
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